CH_EVNT_ERR=Val_0x0, DATA_READ_ERR=Val_0x0, CH_RDWR_ERR=Val_0x0, INSTR_FETCH_ERR=Val_0x0, OPERAND_INVALID=Val_0x0, LOCKUP_ERR=Val_0x0, CH_PERIPH_ERR=Val_0x0, DATA_WRITE_ERR=Val_0x0, UNDEF_INSTR=Val_0x0, ST_DATA_UNAVAILABLE=Val_0x0, DBG_INSTR=Val_0x0
Fault Type for DMA Channel (n) Register
| UNDEF_INSTR | This bit indicates whether the DMA channel thread was attempting to execute an undefined instruction. This fault is a precise abort. 0 (Val_0x0): Defined instruction. 1 (Val_0x1): Undefined instruction. |
| OPERAND_INVALID | This bit indicates whether the DMA channel thread was attempting to execute an instruction operand that was not valid for the configuration of the DMAC. This fault is a precise abort. 0 (Val_0x0): Valid operand. 1 (Val_0x1): Invalid operand. |
| CH_EVNT_ERR | This bit indicates whether the DMA channel thread attempts to execute DMAWFE or DMASEV with inappropriate security permissions. This fault is a precise abort. 0 (Val_0x0): A DMA channel thread in the non-secure state is not violating the security permissions. 1 (Val_0x1): A DMA channel thread in the non-secure state attempted to execute either:
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| CH_PERIPH_ERR | This bit indicates whether a DMA channel thread, in the non-secure state, attempts to execute DMAWFP, DMALDP, DMASTP, or DMAFLUSHP with inappropriate security permissions. This fault is a precise abort. 0 (Val_0x0): A DMA channel thread in the non-secure state is not violating the security permissions. 1 (Val_0x1): A DMA channel thread in the non-secure state attempted to execute either:
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| CH_RDWR_ERR | This bit indicates whether a DMA channel thread, in the non-secure state, attempts to program the DMA_CCRn register to perform a secure read or secure write. This fault is a precise abort. 0 (Val_0x0): A DMA channel thread in the non-secure state is not violating the security permissions. 1 (Val_0x1): A DMA channel thread in the non-secure state attempted to perform a secure read or secure write. |
| MFIFO_ERR | This bit indicates whether the MFIFO prevented the DMA channel thread from executing DMALD or DMAST. Depending on the instruction:
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| ST_DATA_UNAVAILABLE | This bit indicates whether the MFIFO did not contain the data to enable the DMAC to perform the DMAST. This fault is a precise abort. 0 (Val_0x0): MFIFO contains all the data to enable the DMAST to complete. 1 (Val_0x1): Previous DMALDs have not put enough data in the MFIFO to enable the DMAST to complete. |
| INSTR_FETCH_ERR | This bit indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs an instruction fetch. This fault is a precise abort. 0 (Val_0x0): OKAY response. 1 (Val_0x1): EXOKAY, SLVERR, or DECERR response. |
| DATA_WRITE_ERR | This bit indicates the AXI response that the DMAC receives on the BRESP bus, after the DMA channel thread performs a data write. This fault is an imprecise abort. 0 (Val_0x0): OKAY response. 1 (Val_0x1): EXOKAY, SLVERR, or DECERR response. |
| DATA_READ_ERR | This bit indicates the AXI response that the DMAC receives on the RRESP bus, after the DMA channel thread performs a data read. This fault is an imprecise abort. 0 (Val_0x0): OKAY response. 1 (Val_0x1): EXOKAY, SLVERR, or DECERR response. |
| DBG_INSTR | If the DMA channel aborts, this bit indicates whether the erroneous instruction was read from the system memory or from the debug interface. This fault is an imprecise abort but the bit is only valid when a precise abort occurs. 0 (Val_0x0): Instruction that generated an abort was read from system memory. 1 (Val_0x1): Instruction that generated an abort was read from the debug interface. |
| LOCKUP_ERR | This bit indicates whether the DMA channel has locked-up because of resource starvation. This fault is an imprecise abort. 0 (Val_0x0): DMA channel has adequate resources. 1 (Val_0x1): DMA channel has locked-up because of insufficient resources. |